Switch circuit for switching clock signals

ABSTRACT

A switch circuit for switching two clock signals includes a clock generator, a flip-flop and a multiplexer. The clock generator is to generate a reference signal whose cycle is the lowest common multiple of the cycles of the two clock signals. The flip-flop is to generate a selecting signal by taking a control signal from system as an input signal and taking the reference signal as a timing trigger signal. The multiplexer can output a selected clock signal according to the selecting signal in which the selected clock signal and the switched clock signal are synchronous during their entire cycles.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The invention relates to a circuit, and more particularly to a switch circuit for switching clock signals.

(2) Description of the Prior Art

The advance in computer technology, especially in personal computers (PCs), has brought a lot of conveniences to our daily life. Nowadays, a personal computer becomes an inevitable part in our daily living, for a major part of our day-to-day chores such as searching information, gathering news over the network and so on does highly rely on the PC. The personal computer generally includes a motherboard and a plurality of IC chips mounted on the motherboard. For a computer user, quality and stability are the most wanted to a motherboard. Therefore, in order to keep a substantial market share, computer manufacturers have been endeavoring to improve the quality and stability of the motherboard.

On the motherboard, a clock generator is included to provide clock signals for system operation. In early days, clock generators are made by oscillators. However, different frequencies in clock signals are needed for operating the motherboard such that oscillators to generate signals of various frequencies can be seen in distinct areas on the motherboard. In the latest art, these oscillators are integrated into one single chip for providing clock signals with various frequencies. Therefore, upon a request from the system to switch between different clock signals, a 2-to-1 multiplexer 10 (MUX) is introduced to switch clock signals S₁ and S₂ as shown in FIG. 1.

FIG. 2 shows a clock switching timing diagram according to FIG. 1. It is assumed that frequencies of S₁ and S₂ are 200 MHz and 250 MHz, respectively. When the system outputted a control signal C₁ to switch clock signal (S₁ is the original clock signal), the logic level of control signal C₁ would change from “low” to “high” at time “t” such that the output clock signal S₃ can vary from S₁ to S₂ simultaneously.

In an ideal situation, as the multiplexer 10 changed the clock signal at time “t”, the frequency of output clock signal S₃ (maintained at the frequency of S₁ before clock switching at t) is then changed to the frequency of S₂ after the clock switching at t. It should be noted that the duty cycle of the output clock signal S₃ in the timing period of t can no longer remain at 50% (t_(p)>t_(n)). Thus, a glitch is occurred and error functions are followed at where the circuits adopted the defected clock signal as a reference clock signal. Therefore, the present invention provides a design of signal switching circuit so as to maintain a stable signal output at the moment of signal switching.

SUMMARY OF THE INVENTION

Accordingly, it is one object of the present invention to provide a design of signal switching circuit.

It is one more object of the present invention to provide a circuit for switching clock signals.

According to the present invention, the switch circuit for mutually switching two clock signals includes a clock generator, a D flip-flop and a multiplexer. The clock generator is for generating a reference signal and the cycle of the reference signal is the lowest common multiple of the cycle of the aforesaid two clock signals. The D flip-flop who takes a control signal from system as its input signal and the reference signal as its timing trigger signal is for generating a selecting signal. The D flip-flop which can be triggered by a positive edge or a negative edge of a specific clock pulse can be chosen from a group of RS flip-flops, JK flip-flops, master-slave flip-flops, D flip-flops, and T flip-flops. The multiplexer can output a selected clock signal according to the selecting signal in which the selected clock signal and the switched clock signal are synchronous during their entire cycles.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will now be specified with reference to its preferred embodiment illustrated in the drawings, in which

FIG. 1 is a schematic view of a 2-to-1 multiplexer;

FIG. 2 is a timing diagram for switching clock signals of FIG. 1;

FIG. 3 is a schematic view of a preferred embodiment of the present invention;

FIG. 4 is a characteristic table for the D flip-flop;

FIG. 5 is a timing diagram for switching clock signals of FIG. 3; and

FIG. 6 is a schematic view of another embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The invention disclosed herein is to generate clock signals and the cycle of the clock signals is the lowest common multiple of the cycles for switched clock signals. Additionally, a selecting signal generated by a multiplexer is cooperated for controlling the multiplexer to output a correct clock signal. In the following description, numerous details are set forth in order to provide a thorough understanding of the present invention. It will be appreciated by one skilled in the art that variations of these specific details are possible while still achieving the results of the present invention. In other instance, well-known components are not described in detail in order not to unnecessarily obscure the present invention.

FIG. 3 shows a schematic view of a preferred switch circuit in accordance with the present invention. The switch circuit includes a multiplexer 20 and a D flip-flop 30. In this embodiment, two clock signals (S₄ and S₅) are to be switched by a 2-to-1 multiplexer 20 in the switch circuit. A selecting signal C₂ came from the D flip-flop 30 is used to determine the output signal S₆. Consequently, if the logical level of the selecting signal C₂ is “low”, then the clock signal S₄ is outputted from the multiplexer 20. On the contrary, if the logical level of the selecting signal C₂ goes to “high”, then the multiplexer 20 outputs the clock signal S₅ instead.

As shown, the D flip-flop 30 has a input D, a clock signal CK, and a output Q. FIG. 4 shows a characteristic table for the D flip-flop 30 of FIG. 3. In the present embodiment, the D flip-flop 30 is triggered while hitting the positive edge of the clock pulse. That is to say that the input signal is sampled from the input terminal D and sent directly to the output terminal Q as soon as the CK pulse hits the positive edge. As shown in FIG. 4, it is noted that the values in the D and the Q are the same while the CK meets the positive edge of the pulse. Alternatively, in the present invention, the D flip-flop 30 can also be designed to be triggered at the negative edge.

In the embodiment as shown in FIG. 3, the D flip-flop 30 has a control signal SC received from the system as an input signal at D and as a control signal for switching the clock signals. The reference signal CF at CK can be also used to serve as a clock trigger signal for the D flip-flop 30 to generate a selecting signal C₂ so as to control the output S₆ of the multiplexer 20. The reference signal CF can be generated from the clock generator of the system and the cycle of the reference signal CF can be the lowest common multiple of the corresponding cycles of the two clock signals S₄ and S₅. For example, in the case that the cycles of the two clock signals S₄ and S₅ are 5 ns and 4 ns (where fs₄=200 MHz, fs₅=250 MHz) respectively, then the cycle of the reference signals can be set to 20 ns (frequency equivalent to 50 MHz).

FIG. 5 shows a timing diagram for one embodiment of the present invention in switching clock signals. At the starting point, all related signals such as the reference signal CF, the clock signals S₄, S₅, S₆ are reset so that all these signals can be regulated to start at the same time. At time t′, the control signal SC changes from 0 to 1, but the clock trigger signal (also known as the reference signal CF) of the D flip-flop 30 is not at a state meeting the rising edge. Therefore, at time t′, the D flip-flop 30 remains the original state(the selecting signal C₂ remains 0) so that the frequency of the output clock signal S₆ is still equal to the frequency of signal S₄.

At the moment t″, the state of the reference signal CF is at the rising edge and so the output Q of the D flip-flop 30 would follow the input signal SC to change its state from 0 to 1. Meanwhile, the output signal of multiplexer 20 switches from S₄ to S₅ according to the control signal C₂. It should be noted that the cycle of the reference signals CF (T_(CF)=20 ns) is set as the lowest common multiple of the cycles of the two clock signals S₄ and S₅(T_(S4)=5 ns, T_(S5)=4 ns). Hence, the clock signal S₄ and S₅ can proceed their entire cycles synchronously, and the output clock signal S₆ can switch from S₄ to S₅ after one whole cycle of signal S₄.

Practically, the D flip-flop 30 is consisted of several logic gates. As signals passed through the logic gates, propagation delay would be occurred during signal transmission. Therefore, in the present invention, the selecting signal C₂ may be delayed for a period of time before input to the multiplexer 20. Therefore, in order to make sure that the switch circuit can work correctly, the input signals, S₄ and S₅ of the multiplexer 20 must be delayed for the same period of time (used a delay chain 22, 24) so as to meet with the selecting signal C₂.

In the previous embodiment, two clock signals (S₄ and S₅) are used as an example for switching demonstration. On the other hand, as shown in FIG. 6, switching among four clock signals (S₇

S₈

S₉

S₁₀) with a 4-to-1 multiplexer 40 and two D flip-flops 42

44 is illustrated. In this embodiment, SC₁ and SC₂ are two control signals forming four combination to control four clock signals (S₇

S₈

S₉

S₁₀) respectively and CF₁ is the common reference clock signal that the lowest common multiple of cycles of the four signals S₇

S₈

S₉

S₁₀. The control signal SC₁, SC₂ and reference clock signal CF₁ are used to switch these four different clock signals. The switching among signals of this embodiment is resembled to that described above from FIG. 3 through FIG. 5, and so details thereabout will be omitted herein.

In another embodiment of the present invention not shown here, a combination of a 4-to-1 multiplexer, two D flip-flops and two control signals can be used to complete the switching among three clock signals.

Inferred from the aforementioned descriptions, to switch k clock signals, it would need a 2^(n)-to-1 multiplexer and n flip-flops where 2^(n−1)<k ≦2^(n), in which both k and n are natural numbers. Furthermore, the number of control signals should be met with the number (n) of flip-flops. For example, the G-th control signal is the input signal of the G-th flip-flop and the G belongs to the nature number from 1 to n. Besides, the cycle of the reference signals should be the lowest common multiple of the cycles of the k clock signals so as to switch among k signals. It should be noted that the foregoing flip-flops can be selected from a group of RS flip-flops, JK flip-flops, master-slave flip-flops, D flip-flops, and T flip-flops. Definitely, for those skilled in the art, minor modification upon the present invention to meet a practical application is also simply to achieve.

In summary, the switch circuit of the invention provides at least following advantages over the conventional techniques:

-   -   (1) The output clock signal output from the switch circuit of         the present invention could maintain in a stable state that         other circuits adopting the foregoing clock signal as a         reference signal could remain in a normal operating state.     -   (2) The switch circuit of the present invention has advantage in         design to be simply designed and easy to achieve so as to reduce         the degree of difficulty for the motherboard designers.

While the preferred embodiments of the invention have been set forth for the purpose of disclosure, modifications of the disclosed embodiments of the invention as well as other embodiments thereof may occur to those skilled in the art. Accordingly, the appended claims are intended to cover all embodiments which do not depart from the spirit and scope of the invention. 

1. A switch circuit for switching k clock signals, wherein 2^(n−1)≦k≦2 ^(n), both k and n are natural numbers, comprising: a clock generator for generating a reference signal, wherein a cycle of said reference signal is the lowest common multiple of cycles of said k clock signals; n flip-flops for generating n selecting signals by taking a G-th control signal from a system as an input signal of the G-th flip-flop and taking said reference signal as a timing trigger signal for said n flip-flops wherein the G is a natural number between 1 and n; and a multiplexer for outputting a designated clock signal referring to said n selecting signals wherein said designated clock signal is switched after a previous clock signal and said designated clock signal complete their whole cycles synchronously.
 2. The switch circuit according to claim 1, wherein said flip-flop is selected from a group of RS flip-flops, JK flip-flops, master-slave flip-flops, D flip-flops, and T flip-flops.
 3. The switch circuit according to claim 1, wherein said flip-flop is a positive edge trigger flip-flop.
 4. The switch circuit according to claim 1, wherein said flip-flop is a negative edge trigger flip-flop.
 5. The switch circuit according to claim 1, wherein said multiplexer is a 2^(n)-to-1 multiplexer.
 6. A switch circuit for switching k clock signals, wherein 2^(n−1)<k≦2 ^(n), both k and n are natural numbers, comprising: a clock generator for generating a reference signal, wherein a cycle of said reference signal is the lowest common multiple of cycles of said k clock signals; n D flip-flops for generating n selecting signals by taking a G-th control signal from a system as an input signal of the G-th D flip-flop and taking said reference signal as a timing trigger signal for said n D flip-flops wherein the G is a natural number between 1 and n; and a multiplexer for outputting a designated clock signal referring to said n selecting signals wherein said designated clock signal is switched after a previous clock signal and said designated clock signal complete their whole cycles synchronously.
 7. The switch circuit according to claim 6, wherein said D flip-flop is a positive edge trigger D flip-flop.
 8. The switch circuit according to claim 6, wherein said D flip-flop is a negative edge trigger D flip-flop.
 9. The switch circuit according to claim 6, wherein said multiplexer is a 2^(n)-to-1 multiplexer.
 10. A switch circuit for mutually switching two clock signals, comprising: a clock generator for generating a reference signal, wherein a cycle of said reference signal is the lowest common multiple of cycles of said two clock signals; a D flip-flop for generating a selecting signal by taking a control signal from a system as an input signal and taking said reference signal as a timing trigger signal; and a multiplexer for outputting a designated clock signal referring to said selecting signal wherein said designated clock signal is switched after a previous clock signal and said designated clock signal complete their whole cycles synchronously.
 11. The switch circuit according to claim 10, wherein said D flip-flop is a positive edge trigger D flip-flop.
 12. The switch circuit according to claim 10, wherein said D flip-flop is a negative edge trigger D flip-flop.
 13. The switch circuit according to claim 10, wherein said multiplexer is a 2-to-1 multiplexer. 